As ground rules continue to shrink for devices in new technologies, device isolation regions called shallow trench isolation (STI) features have become increasingly popular as a means of separating active regions from one another. Devices such as transistors, resistors, and diodes are formed on active regions of a substrate. Increasing circuit density and improving device performance not only require that individual components of a device shrink in size but that the shallow trench isolation features are also reduced in dimension, especially the width or distance between adjacent active regions.
Each pattern that is formed in a substrate is typically first printed in a photoresist layer by a lithographic process involving an exposure followed by developing in an aqueous base solution. Selected portions of the photoresist are removed to expose an underlying layer and the remaining photoresist layer serves as an etch mask while the pattern is transferred into the substrate to form lines and spaces, for example. Typically, the pattern is complex and contains isolated, semi-isolated, and dense features in various arrays. A variation of a line/space pattern is a trench which may have a width that ranges from about 0.1 microns to greater than 10 microns. One version of a trench pattern is a shallow trench that has a depth of approximately 3000 to 4000 Angstroms (0.3–0.4 microns). The width of the active region between shallow trenches may have a similar range of sizes as the trench. Generally, an oxide liner is grown on the sidewalls and bottom of a trench as a means of preventing dopant in adjacent source/drain regions from migrating into the STI features and rounds the adjacent silicon device edge to minimize leakage current.
A necessary result of shallow trench isolation (STI) fabrication is that the insulating material which fills the shallow trench should form a smooth surface after a planarization step. This condition ensures that a subsequent step such as patterning a photoresist to form a template for a gate layer in a transistor device will have an optimum focus and exposure latitude. However, a high density plasma (HDP) chemical vapor deposition (CVD) step that is often used to deposit an oxide insulating layer into a shallow trench is known to form a thicker insulating layer in portions of a shallow trench pattern that have densely packed trenches with small opening widths while forming a thinner insulating layer in wide shallow trenches. A subsequent planarization process involving a chemical mechanical polish (CMP) step cannot compensate for the thickness variation and causes a dishing or bowl shaped indentation in the insulating layer formed within wide shallow trenches. The problem is not easily corrected and expensive rework steps may result. Therefore, an improved STI fabrication method that overcomes oxide thickness variations in a pattern having different opening widths is needed.
In U.S. Pat. No. 5,494,857, a polish assist layer is deposited on an oxide filler layer in an STI scheme. A photoresist is patterned on the polish assist layer and etched to form blocks of the assist layer in large depressions. The assist blocks enable a CMP step to form a planar surface on the oxide fill layer that is independent of pattern density.
An STI method is described in U.S. Pat. No. 6,258,692 in which a buffer layer such as silicon nitride is deposited on a mask layer and in a shallow trench followed by deposition of a SiO2 insulating layer to fill the trench. The SiO2 layer is partially removed by a CMP step and then an etch back removes the buffer layer and SiO2 above the level of the shallow trench to leave a planar surface.
In U.S. Pat. No. 6,319,796, a first dielectric layer is formed over a shallow trench pattern by a HDP CVD method. The HDP CVD method is continued with a different deposition/etch ratio to give a second dielectric layer on the first dielectric layer. The thickness of the combined dielectric layers may be adjusted to minimize thickness variation over trenches with different widths.
An STI method is described in U.S. Pat. No. 6,232,043 that involves partial etching of an HDP CVD layer over an active region before a CMP is performed. The oxide thickness to be removed during CMP is determined by the % of active area and the % of etched area relative to total wafer area. However, the method is not applicable when the width of the active region shrinks to about 0.13 micron or less. A similar STI method is described in U.S. Pat. No. 6,242,322 where a HDP CVD oxide is deposited to fill wide and narrow trenches and a wide island between the trenches. A polysilicon layer is deposited on the HDP CVD oxide followed by a selective CMP step to form a self-align reverse poly mask which exposes only the oxide on the wide island. A large portion of the exposed oxide is removed by a selective etch and then a second CMP step planarizes the oxide layer.
Two step deposition processes are described in U.S. Pat. Nos. 6,573,152 and 6,211,040 in which a first portion of a dielectric layer is deposited in a HDP CVD process with a first etch/deposition (E/D) ratio and a second portion of the dielectric layer is deposited with a second E/D ratio that is higher than the first E/D ratio. However, these prior art methods do not address the issue of different size trenches or trenches with different pattern densities that need to be filled to the same level.